The present invention relates to a method of producing a memory management table that has control over memories having a function to hold data at a time of power cut-off and manages identifier information of memory areas to be data storage destinations designated by a logical address issued by a host device, and to a memory device for which the method is employed. More particularly, the present invention relates to a method of producing a memory management table that reduces the start-up time of a memory device and ensures a system to start a normal operation, and to a memory device for which the method is employed.
When a non-volatile memory such as a flash memory, a FRAM, or a EEPROM, or a memory such as a RAM backed up by a battery is mounted on a memory card or the like, it is necessary to create a memory management table for managing the correspondence between the logical addresses of data and physical addresses so as to carry out an access request issued by a host computer.
A flash memory, for instance, is divided into 512 blocks that serve as data erase units, as shown in FIG. 1. Each of the blocks has eight sectors that serve as data storing units. The data stored in each sector (constituted by 512 bytes, for instance) is provided with a logical address issued by the host computer. As shown in FIG. 2, identical logical addresses are allocated to the data stored in one block.
A memory management table is prepared to manage the correspondence between logical addresses and block numbers so as perform a process of converting a logical address into a physical address. Referring now to FIGS. 3 and 4, an example case where four flash memories are mounted will be explained below.
In the memory management table shown in FIG. 3, there is a prerequisite that the data having logical addresses xe2x80x9c0xe2x80x9d, xe2x80x9c4xe2x80x9d, . . . are stored in the flash memory having a chip number xe2x80x9c0xe2x80x9d, the data having logical addresses xe2x80x9c1xe2x80x9d, xe2x80x9c15xe2x80x9d, . . . are stored in the flash memory having a chip number xe2x80x9c1xe2x80x9d, the data having logical addresses xe2x80x9c2xe2x80x9d, xe2x80x9c6xe2x80x9d, . . . are stored in the flash memory having a chip number xe2x80x9c2xe2x80x9d, the data having logical addresses xe2x80x9c3xe2x80x9d, xe2x80x9c7xe2x80x9d, . . . are stored in the flash memory having a chip number xe2x80x9c3xe2x80x9d, the data having logical addresses. The part of the table corresponding to the flash memory of the chip number xe2x80x9c0xe2x80x9d manages the storing destination block number of the logical address xe2x80x9c0xe2x80x9d, the storing destination block number of the logical address xe2x80x9c4xe2x80x9d, and so forth. The part of the table corresponding to the flash memory of the chip number xe2x80x9c1xe2x80x9d manages the storing destination block number of the logical address xe2x80x9c1xe2x80x9d, the storing destination block number of the logical address xe2x80x9c5xe2x80x9d, and so forth. The part of the table corresponding to the flash memory of the chip number xe2x80x9c2xe2x80x9d manages the storing destination block number of the logical address xe2x80x9c2xe2x80x9d, the storing destination block number of the logical address xe2x80x9c6xe2x80x9d, and so forth. The part of the table corresponding to the flash memory of the chip number xe2x80x9c3xe2x80x9d manages the storing destination bloc number of the logical address xe2x80x9c3xe2x80x9d, the storing destination block number of the logical address xe2x80x9c7xe2x80x9d, and so forth.
When an access request that specifies a logical address is issued from the host computer in accordance with the memory management table having the above data structure, the physical address of the access destination can be determined by pinpointing the chip number and the block number designated by the logical address.
The blocks in the flash memory are sequentially accessed so as to detect the block number of the block that stores data. Also, the logical address allocated to the data is detected, and the detected block number is stored in the entry designated by the logical address in the management table. In this manner, the memory management table is produced.
In a case where a non-volatile memory or a memory backed up by a battery is mounted on a conventional memory card, an initializing process is performed by setting an initial value in each inner register when the memory is started by switching the power on. After that, the memory is accessed so as to produce a memory management table.
When the memory management table is completed, the host device is notified of canceling of a busy state, thereby allowing the host device to issue a process request.
In the prior art, however, when the memory is started, the host device of notified of canceling of the busy state only after the completion of the memory management table. With such a structure, there is a problem that the host device cannot promptly start an operation, because it takes time to complete the memory management table.
This adds to another problem that, if a memory card at an access destination is not promptly started, the host device might wrongly detect an error in the memory card.
The present invention relates to a method of producing a memory management table for controlling memories having a function to hold data at a time of power cut-off and managing identifier information of memory areas to be data storage destinations designated by a logical address issued from a host device. The principal object of the present invention is to provide a method of producing a memory management table that can shorten the start-up period of time of a memory device and ensure accurate operations of a system, and also to provide a memory device for which the method of producing a memory management table can be performed.
To achieve the above object, the present invention provides a method of producing a memory management table which serves to control one or a plurality of memories having a function to hold data while the power is cut off, and manages identifier information of memory areas which are data storage destinations each indicated by a logical address issued by a host device. This method includes the steps of:
notifying the host device of canceling of a busy state;
starting the production of an incomplete part of the memory management table;
accessing the one or the plurality of memories until a process request is issued from the host device, with the memory areas being units, so as to acquire a logical address held by data stored in an accessed one of the memory areas; and
completing the incomplete part of the memory management table based on the acquired logical address and the identifier information of the accessed one of the memory areas.
By this method of producing a memory management table, the host device can start an operation immediately after the memory device is activated, thereby shortening the start-up time of the memory device.